Automotive MCU Chip Architect

Hop - Duesseldorf - original posting ->
Status
Open
Remote policy
Not stated
Employment type
Full-time
Salary
Not stated
Categories
Software Engineer
Tech
software
Source
arbeitnow
First observed
2026-10-25 05:14 UTC
Last seen
2026-10-25 05:14 UTC
Source claims posted
2026-10-25 03:07 UTC
Consecutive misses
0 of 3

What the posting says

We are looking for an experienced Automotive MCU Chip Architect to define the system and subsystem architecture of next-generation automotive microcontrollers. The role includes ownership of chip-level architecture concepts, subsystem partitioning, compute and memory architecture, interconnect strategy, safety and security integration, power/reset/clock concepts, and hardware/software interface definition. The successful candidate will work closely with product management, safety, security, design, verification, software, and implementation teams to ensure the MCU architecture meets demanding automotive

requirements for real-time performance, functional safety, cybersecurity, reliability, scalability, and cost efficiency.

What you'll do

Key Responsibilities

System Architecture Definition

Define the overall automotive MCU architecture from product, customer, and market requirements.

Translate use cases into chip-level requirements covering performance, safety, security, power, cost, and

scalability.

Drive system partitioning across CPUs, memories, interconnects, peripherals, safety/security functions,

debug, test, and power domains.

Own architecture trade-offs and document decision rationale for reuse across MCU families and

derivatives.

Subsystem Architecture Ownership

Align subsystem concepts and interfaces across compute, memory, bus/interconnect, peripheral, safety,

security, power/reset/clock, debug/trace, and DFT/test domains.

Ensure subsystem requirements are implementation-feasible and verifiable at RTL, subsystem, chip,

silicon, and software levels.

Define hardware/software-visible architecture elements such as memory maps, register model

principles, interrupts, DMA, boot flow, and access-control concepts.

Cross-Functional Technical Leadership

Lead architecture reviews and resolve trade-offs between product management, system engineering,

safety, security, design, verification, software, backend, test, and validation teams.

Provide technical guidance during concept, design, verification, silicon bring-up, qualification, and

customer support phases.

Ensure architectural consistency, requirement traceability, and risk closure across global engineering

teams.

What we require

Required Technical Expertise

MCU / SoC Architecture

Deep understanding of real-time MCU architectures, CPU subsystems, memories, peripheral integration,

low-power design, product-family scalability, and silicon implementation constraints.

Automotive Functional Safety

Practical ISO 26262 expertise including ASIL concepts, safety goals, technical safety requirements,

FMEDA/DFA/FTA awareness, and definition of safety mechanisms at system and subsystem level.

Automotive Cybersecurity

Understanding of secure boot, hardware root of trust, HSM integration, cryptographic accelerators, key

management, lifecycle states, secure debug, and ISO/SAE 21434 concepts.

Digital Design and Implementation Awareness

Ability to reason about RTL feasibility, timing, area, power, DFT, backend constraints, IP integration,

verification closure, and bring-up observability.

Embedded Software Awareness

Working knowledge of startup software, boot flows, drivers, AUTOSAR concepts, RTOS use, interrupts,

memory protection, debug, and software-visible register behavior.

Required Experience

10+ years in semiconductor, MCU, SoC, or embedded systems development.

Several years in system architecture, subsystem architecture, or senior technical leadership.

Hands-on experience with automotive MCU or automotive SoC products.

Experience across concept definition, architecture specification, design support, verification support,

silicon bring-up, qualification, and customer support.

Proven ability to work with international and cross-functional engineering teams.

Quality

Completeness: 45%

Not enough history yet to judge honesty signals.

Timeline

  1. *
    #1532274 2026-10-25 05:14 UTC
    Published