FPGA Engineer (Controls & Signal Processing)

Status
Open
Remote policy
Not stated
Employment type
Full-time
Salary
Not stated
Categories
Technical Staff
Tech
rustembedded
Source
arbeitnow
First observed
2026-09-27 11:42 UTC
Last seen
2026-09-27 11:42 UTC
Source claims posted
2026-09-27 10:04 UTC
Consecutive misses
1 of 3

What the posting says

About Enact

The next defining technological breakthrough will be in the physical world. We stand at a historical inflection point: bringing general-purpose intelligence into robotics.

At Enact we rethink the entire robotic tech stack from model architectures and data pipelines, to the actuators and sensors that feed the model. Pushing beyond pure vision and language approaches, we build a proprioceptive nerve system, and the cortex that makes sense of it, to solve dexterity through whole-body force-awareness and deploy robots for thousands of tasks in industry and beyond.

We are shaping a company where brilliant and unconventional people thrive together on solving the hardest challenges of our time. We are truth seekers. We reason from first principles, test our beliefs against reality, and trust that the best ideas can come from anyone. We move fast. We care deeply about our work and colleagues and are driven by passion to change the status quo.

If this resonates, we're excited to hear from you.

In This Role You Will

Design, implement, and verify the FPGA fabric at the heart of our custom hardware, from real-time control and signal processing to high-speed sensor and data interfaces.

Own the build flow: synthesis, place & route, static timing analysis, and timing closure on real silicon.

Develop testbenches, simulation, and co-simulation to verify behaviour at unit and system level.

Take designs from RTL through board bring-up, integration, and lab debug under real operating conditions all the way through to production-ready.

Keep the design understandable: specifications, timing budgets, and verification plans.

What We're Looking For

Strong digital design fundamentals: RTL in SystemVerilog (or VHDL), and a solid grasp of computer architecture.

The ability to reason about fixed- and floating-point data paths and pipelines - where precision goes, where it costs you, and how a computation maps onto real hardware.

Experience closing timing: static timing analysis, writing constraints, clock-domain crossing, and synchronization.

Fluency with at least one vendor toolchain (Xilinx/AMD, Intel/Altera, or Lattice), in a heavily scripted setting.

Comfortable reading schematics, reasoning from first principles, and working shoulder-to-shoulder with electronics and mechanical engineers.

The ability to take designs from benchtop prototype to production ready.

Fluency in English (German not required, though useful!).

Bonus Points If You Have

Having done these before is a plus, not a prerequisite. You'll do much of it in the role:

Rust or embedded firmware experience.

DSP in fabric: filtering (FIR/IIR), FFT, and fixed-point implementation.

Control theory: system identification, plant modeling, and loop tuning.

High-speed ADC/DAC interfaces and sensor/communication protocols.

Expert knowledge of version control, especially git.

Safety-critical or certified design.

Experience collaborating across analog, software, and mechanical domains.

What We Offer

The opportunity to make a real impact working on some of the biggest challenges of our time

A fast-paced learning environment alongside an outstanding, driven team

Ownership from day one, with the ability to iterate quickly and see your impact firsthand in an early-stage startup

Visa sponsorship & relocation benefits to hire the best in the world

A world-class in-person setup in central Zürich, with excellent prototyping, robotics, and technical infrastructure for hands-on builders

Competitive compensation and meaningful equity participation

Find more English Speaking Jobs in Switzerland on Arbeitnow

Quality

Completeness: 45%

Not enough history yet to judge honesty signals.

Timeline

  1. *
    #1030172 2026-09-27 11:42 UTC
    Published
  2. o
    #1031180 2026-09-27 12:49 UTC
    Not seen
    Miss 1 in a row