Physical Verification Engineer

About us

Salience Labs is building an industry-defining approach to optical circuit switching for AI infrastructure, engineered for real latency reduction and cost savings. We're moving towards real-world deployment, and joining at this stage means genuine ownership over that next chapter, working alongside a highly technical team on one of the most consequential problems in AI infrastructure today.

About the Role

We’re looking for a Physical Verification Engineer to drive DRC/LVS signoff for our integrated circuit and photonic integrated circuit (PIC) designs. You’ll work at the intersection of electronic and photonic design, running and debugging verification flows against foundry PDKs and helping keep our tapeouts clean.

What You’ll Do

Run and debug physical verification (DRC, LVS, extraction) on IC and photonic IC layouts

Debug LVS/DRC discrepancies, including port mismatches, hierarchy mismatches, and device recognition issues

Read, manipulate, and QA GDS/OASIS layout data

Maintain and extend verification runsets and rule decks

Build Python/Tcl/shell tooling to automate verification flows and triage error reports

Maintain verification libraries and runsets under version control, with controlled release processes

Handle third-party and foundry IP with care, following licensing terms

Work with design, layout, and CAD teams to close out verification issues ahead of tapeout

Document known issues, workarounds, and runset changes

What You Bring

Required

3+ years of hands-on physical verification experience in IC design

Practical experience with Siemens Calibre and/or Synopsys ICV for DRC/LVS signoff

Experience with custom/analog layout tools such as Cadence Virtuoso or Synopsys CustomCompiler

Strong working knowledge of GDS/OASIS formats and LVS concepts

Proficiency with Linux and scripting in Python, Tcl, or shell

Experience managing rule decks, runsets, or libraries under version control (e.g., Git)

Ability to independently debug complex hierarchical netlist and layout issues

Strong written communication for documenting root causes and fixes

Nice to have

Photonic IC verification experience

Experience with Verilog/SystemVerilog netlists

Exposure to foundry PDK qualification

Experience building internal automation to scale verification